A high frequency semiconductor device in which FET chips including, for example, a plurality of field effect transistor (FET) cells are arranged in parallel in a package has an input/output matching circuit in the package. An input matching circuit includes a dividing circuit and a parallel capacitor in which a plurality of capacitors is arranged in parallel and an output matching circuit includes a combining circuit and a similar parallel capacitor.
When a high frequency is input into such a high frequency semiconductor device, the high frequency is distributed into a plurality of high frequencies by a dividing line and each distributed high frequency is input into each cell of the FET chip via each capacitor of the parallel capacitor. Each of the plurality of high frequencies output from each cell of a plurality of FET chips is input into a combining line via each capacitor of the parallel capacitor before being synthesized and output.
FIG. 19 is a schematic plan view when a conventional parallel capacitor is viewed from above. As shown in FIG. 19, a conventional parallel capacitor 2000 applied to each matching circuit described above includes a plurality of capacitors 2011 configured by providing a plurality of upper electrodes 2013 mutually having an equal area on the surface of a dielectric substrate 2012 like being spaced from each other and also providing a lower electrode 1014 on an underside of the dielectric substrate 2012.
FIGS. 20A, 20B, and 20C are each schematic sectional views of the conventional parallel capacitor along an alternate long and short dash line X-X′ in FIG. 19. In FIGS. 20A, 20B, and 20C, reference numeral 2011e is attached to, among the plurality of capacitors 2011 shown in FIG. 19, the capacitors 2011 on both ends and reference numeral 2011c is attached to the capacitors 2011 in the center portion sandwiched between the capacitors 2011e on both ends. Similarly, reference numeral 2013e is attached to, among the plurality of upper electrodes 2013, the upper electrodes 2013 arranged on both ends of the dielectric substrate 2012 and reference numeral 2013c is attached to the upper electrodes 2013 arranged in the center portion sandwiched between both ends of the dielectric substrate 2012.
As shown in FIGS. 20A and 20B, the capacities of the capacitors 2011e, 2011c when a high frequency output from an RF power supply 15 is applied to, among the plurality of upper electrodes 2013e, 2013c, only one upper electrode, will be called single-operation capacities Ces, Ccs. For example, as shown in FIG. 20A, the capacity of the capacitor 2011e when a high frequency is applied to only the upper electrode 2013e on the left end in FIG. 20A is called the single-operation capacity Ces and, as shown in FIG. 20B, the capacity of the capacitor 2011c when a high frequency is applied to only the upper electrode 2013c in the center portion in FIG. 20B is called the single-operation capacity Ccs. As shown in FIG. 20C, the capacities of the capacitors 2011e, 2011c when a high frequency output from the RF power supply 15 is simultaneously applied to all of the plurality of upper electrodes 2013e, 2013c will be called simultaneous-operation capacities Cep, Ccp.
FIGS. 21A and 21B are each explanatory views illustrating the single-operation capacity of each capacitor constituting a conventional parallel capacitor and FIG. 21C is an explanatory view illustrating the simultaneous-operation capacity of each capacitor constituting the conventional parallel capacitor.
If, as shown in FIG. 21A, a high frequency output from the RF power supply 15 is applied to only the upper electrode 2013e on the left end of the parallel capacitor 2000, an electric line of force E extends up to the neighboring capacitor 2011c on one side of the capacitor 2011e to which the high frequency is applied and so-called coupling occurs, generating a coupling capacity Ce-cup. Further, the electric line of force E swells in an outer direction on the other end of the capacitor 2011e to which the high frequency is applied, generating a so-called fringing capacity Ce-fringe. As a result, the single-operation capacity of the capacitor 2011e increases only by the coupling capacity Ce-cup and the fringing capacity Ce-fringe from the original capacitor capacity Ce. The original capacitor capacity Ce means the capacity determined by an area Se of the upper electrode 2013e without including the coupling capacity Ce-cup and the fringing capacity Ce-fring. The original capacitor capacity Cc described below also has the same meaning.
If, as shown in FIG. 21B, a high frequency output from the RF power supply 15 is applied to only the upper electrode 2013c in the center of the parallel capacitor 2000, the electric line of force E extends up to the neighboring capacitors 2011c, 2011e on both sides of the capacitor 2011c to which the high frequency is applied and so-called coupling occurs, generating a coupling capacity Cc-cup. As a result, the single-operation capacity of the capacitor 2011c increases only by the coupling capacity Cc-cup from the original capacitor capacity Cc.
If a high frequency is applied to only the upper electrode 2013c in the center of the parallel capacitor 2000, the upper electrodes 2013c, 2013e contributing to coupling are arranged on both sides of the upper electrode 2013c to which the high frequency is applied and thus, the coupling capacity Cc-cup may be larger than the coupling capacity Ce-cup. Particularly when the upper electrodes 2013c, 2013e are arranged close to each other, the coupling capacity Cc-cup becomes larger than the total of the coupling capacity Ce-cup and the fringing capacity Ce-fringe.
In the conventional parallel capacitor 2000, therefore, even if the plurality of upper electrodes 2013e, 2013c having the mutually equal area is provided, the single-operation capacity of the capacitor 2011e on both ends and the single-operation capacity of the capacitor 2011c in the center portion may be different.
If, as shown in FIG. 21C, a high frequency output from the RF power supply 15 is simultaneously applied to all the upper electrodes 2013e, 2013c of the parallel capacitor 2000 (all the capacitors 2011e, 2011c are simultaneously operated), the upper electrode 2013e and the upper electrode 2013c are at the same potential and therefore, the electric line of force E as illustrated in FIG. 21C is generated in the dielectric substrate 2012.
That is, the electric line of force E extending linearly from the upper electrode 2013e toward the lower electrode 2014 is generated in the capacitor 2011e on both sides. Further, the electric line of force E swelling in the outer direction of the capacitor 2011e is also generated. Therefore, the simultaneous-operation capacity Cep of the capacitor 2011e increases only by the fringing capacity Ce-fringe from the original capacitor capacity Ce.
In the capacitor 2011c in the center portion, the upper electrode 2013c of the capacitor 2011c is close to the surrounding upper electrodes 2011c, 2011e and thus, only the electric line of force E extending linearly from the upper electrode 2013c toward the lower electrode 2014 is generated, and the electric line of force E swelling in the outer direction is hardly generated. Therefore, the simultaneous-operation capacity Ccp of the capacitor 2011c approximates to the original capacitor capacity Cc.
In the conventional parallel capacitor 2000, therefore, even if the plurality of upper electrodes 2013e, 2013c having the mutually equal area is provided, the simultaneous-operation capacity of the capacitor 2011e on both ends and the simultaneous-operation capacity of the capacitor 2011c in the center portion may be different.
If the spacing of the upper electrodes 2013e, 2013c is made sufficiently wider than the thickness of the dielectric substrate 2012, the electric line of force E swelling in the outer direction of the capacitor 2011c is also generated in the capacitor 2011c in the center portion. Therefore, the simultaneous-operation capacity Ccp of the capacitor 2011c increases only by the fringing capacity Ce-fringe from the original capacitor capacity Cc.
In general, however, the plurality of capacitors 2011c, 2011e is arranged in spacing substantially equal to the spacing of a plurality of FET cells constituting a FET chip and thus, the spacing of the upper electrodes 2013e, 2013c is narrower than the thickness of the dielectric substrate 2012.
Therefore, as has been described with reference to FIG. 21C, in the conventional parallel capacitor 2000, the simultaneous-operation capacity Cep of the capacitor 2011e on both ends and the simultaneous-operation capacity Ccp of the capacitor 2011c in the center portion may be different.
In a conventional high frequency semiconductor device having the conventional parallel capacitor 2000 as described above, power of an output high frequency may be smaller than desired power. One of the causes therefor is considered to be differences of the simultaneous-operation capacities Ccp, Cep of the plurality of capacitors 2011c, 2011e constituting the conventional parallel capacitor 2000. If there are differences of the simultaneous-operation capacities Ccp, Cep of the capacitors 2011c, 2011e, a phase shift of a high frequency output from each of the capacitors 2011c, 2011e arises. High frequencies are synthesized in a mutually phase-shifted state by a combining circuit of an output matching circuit and therefore, output power of high frequency decreases.